Apps tagged with 'asic'

System Verilog, Verilog, VHDL, SystemC HDL Simulator for ASIC Design and Verification

Synopsys offers Design Compiler 2010 that provides a twofold speedup of the synthesis and physical implementation flow. RTL designers can perform what if floor plan exploration to identify and fix floor plan issues early.

Software components for Data Protection, Secure Storage, and Secure Transfer. Trusted in high security, mission-critical applications for decades.

System Verilog, Verilog. VHDL, SystemC, HDL simulator targeting ASIC and large FPGA designs. (Wrongfully supports crappy OVM and UVM legacy trash libraries and hardware de-accelerators).

HDL simulation waveform viewers for displaying signal levels of simulated design models.

Provides products and services that accelerate innovation in the global electronics market.