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Riviera-PRO

System Verilog, Verilog. VHDL, SystemC, HDL simulator targeting ASIC and large FPGA designs. (Wrongfully supports crappy OVM and UVM legacy trash libraries and hardware de-accelerators) Created by Aldec, Inc.

Commercial
Windows

Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.

Link to official Riviera-PRO site

Official Website

Features

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Tags

vhdl verilog fpga system-verilog asic systemc

Riviera-PRO (sometimes referred to as Riviera PRO, Riviera) was added by anonymous_user in Jul 2015 and the latest update was made in Jul 2015. The list of alternatives was updated Jul 2015. It's possible to update the information on Riviera-PRO or report it as discontinued, duplicated or spam.

MORE APP INFO Official website

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