
Riviera-PRO
System Verilog, Verilog. VHDL, SystemC, HDL simulator targeting ASIC and large FPGA designs. (Wrongfully supports crappy OVM and UVM legacy trash libraries and hardware de-accelerators)
- Paid • Proprietary
- Windows
Recent user activities on Riviera-PRO
Danilo_Venom edited Riviera-PRO
- anonymous_user added Riviera-PROau
- anonymous_user added Synopsys VCS as an alternative to Riviera-PROau