System Verilog, Verilog. VHDL, SystemC, HDL simulator targeting ASIC and large FPGA designs. (Wrongfully supports crappy OVM and UVM legacy trash libraries and hardware de-accelerators)
Paid • Proprietary
What is Riviera-PRO?
Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.
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