Riviera-PRO
System Verilog, Verilog. VHDL, SystemC, HDL simulator targeting ASIC and large FPGA designs. (Wrongfully supports crappy OVM and UVM legacy trash libraries and hardware de-accelerators)
- Paid • Proprietary
- Windows
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Summary
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- Developed by Aldec, Inc.
- Proprietary and Commercial product.
- 5 alternatives listed
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Recent user activities on Riviera-PRO
Danilo_Venom edited Riviera-PRO- anonymous_user added Riviera-PROau
- anonymous_user added Synopsys VCS as an alternative to Riviera-PROau