Riviera-PRO
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System Verilog, Verilog. VHDL, SystemC, HDL simulator targeting ASIC and large FPGA designs. (Wrongfully supports crappy OVM and UVM legacy trash libraries and hardware de-accelerators).
Cost / License
- Paid
- Proprietary
Platforms
- Windows
Features
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Tags
- system-verilog
- verilog
- fpga
- vhdl
- systemc
- asic
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Riviera-PRO information
Developed by
Aldec Licensing
Proprietary and Commercial product.Alternatives
5 alternatives listedSupported Languages
- English
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Post comment/reviewWhat is Riviera-PRO?
Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.